A conventional memory, for example, a DRAM, may include one transistor and one capacitor. However, there are limitations to the scalability of a conventional memory, due to the presence of the capacitor and, in particular, the size of the capacitor. As a result, memories including one transistor (IT) and no capacitor as a memory cell, referred to as “capacitor-less” memories, have been developed. A capacitor-less memory cell may include a floating body (i.e., a body that is electrically floated).
Generally, a conventional capacitor-less memory cell utilizes a silicon-on-insulator (SOI) wafer and identifies data controlling the floating body voltage by accumulating a majority carrier (either holes or electrons) in a floating body or by emitting the majority carrier from the floating body. As understood by a person having ordinary skill in the art, a logic “1” may be written to and stored in a memory cell by causing majority carriers to accumulate and be held in the floating body. As such, when the majority carrier is accumulated in the floating body, this state is generally referred to as a data “1” state. A logic “1” may be erased (i.e., logic “0” is written) by removing the majority carriers from the floating body. As such, when the majority carrier is evacuated from the floating body, this state is generally referred to as a data “0” state. As also understood by a person having ordinary skill in the art, the stored charge in the transistor floating body affects the threshold voltage (VT) of the memory cell transistor. A lower threshold voltage (VT) increases the current through the memory cell transistor, and a higher threshold voltage (VT) decreases the current though the transistor. The current through the memory cell transistor is used to determine the state of the memory cell.
FIG. 1 illustrates an example of a conventional floating body memory cell 10. Memory cell 10 includes a transistor 12 having a gate region 16, a source region 18, and a drain region 20. Source region 18 and drain region 20 are formed in silicon layer 26 with a floating body region 24 being defined therebetween. Moreover, floating body region 24 is disposed on an insulating layer 28 which overlies a substrate 30. Memory cell 10 also includes a region 38 comprising silicon which is highly positively doped compared to floating body region 24, but less positively doped than source region 18 or drain region 20. Region 38 is connected to a contact 40 by means of conductive line 41 passing through insulating layer 28, silicon layer 26, and an insulating layer 32. By applying a negative voltage to region 38, typically in the region of −20V for insulation layer 28 having a thickness of 400 nanometers, a neutral zone may be formed in floating body region 24. Therefore, it is possible to generate and store an electrical charge within floating body region 24.
As illustrated above, a conventional floating body memory cell stores charges within a floating body that is adjacent to the drain and source regions and, therefore, the stored charges have a tendency to leak out of the floating body during operation. This is particularly an issue during operations at higher temperatures. Additionally, conventional floating body memory cells suffer from poor data retention due to charge lost from the floating body upon charge recombination during hold, read, and write operations. Furthermore, because conventional floating body memory cells may have a small floating body which is not configured to hold a substantial charge, any charge lost may result in a fluctuating or weakened signal.
There is a need for methods, devices, and systems for enhancing the functionality of floating body memory cells. Specifically, there is a need for methods, devices, and systems for enhancing the functionality of a memory cell by increasing the size of a floating body of a memory cell and increasing data retention by a floating body memory cell.